SAN DIEGO, Sept. 14, 2022 (GLOBE NEWSWIRE) — GBT Technologies Inc. (OTC PINK: GTCH) (“GBT” or the “Company”) has been granted a fast track application by the United States Patent and Trademark Office for its non-provisional patent application relating to the automatic correction of mismatches in the electrical connectivity of integrated circuits (IC). The patent application is subjected to a prioritized examination in order to speed up the process. The original patent was filed on August 3, 2022 (Application No. 17880055) to protect programmatic methods and algorithms for automatically correcting mismatches in electrical connectivity in integrated circuits with the aim of shortening the design cycle of microchips, especially for advanced ones Nanometer nodes of 5nm and below.

The layout versus schematic (LVS) verification process compares the IC mask to the schematic netlist to see if they match. The comparison results are considered “pass” (or “clean”) when all electronic devices and connectivity described in the schematic match the devices and connectivity in the layout. A “Fail” (or “Dirty”) result means that the connectivity and/or devices do not match. Especially with analog or MIXED layout types, these mismatches would have to be fixed manually, which is a tedious, time-consuming manual design work. A layout designer would need to debug the results, identify the incorrect electrical connections and/or device mismatches, and make the necessary layout modifications to achieve a “clean” comparison.

GBT’s non-provisional patent application seeks to protect an algorithmic system and method for automatically performing this process. With the click of a button, the system reads the IC’s schematic and layout data, compares the devices and electrical connectivity (wiring), and in the event of a mismatch, disconnects the faulty wires and reconnects them in the layout to achieve a “clean” LVS. The system is designed to automatically correct the layout without letting other…